In the semiconductor device field in which scaling is advanced, various kinds of low dielectric constant materials (hereinafter, referred to as “low-k materials” in some cases) having a porous structure have been investigated as an interlayer dielectric layer of semiconductor.
If the porosity of the semiconductor interlayer dielectric layer having a porous structure is increased in order to further lower the dielectric constant thereof, metal components such as copper, which is embedded as a wiring material, or plasma components (at least one of radical or ion, the same shall apply hereinafter) caused by plasma treatment are prone to enter into the pores in the semiconductor interlayer dielectric layer, and thus the dielectric constant thereof increases or leakage current occurs in some cases.
In addition, metal components or plasma components diffuse even into a non-porous interlayer dielectric layer in some cases, and thus dielectric constant increases or leakage current occurs in the same manner as in a porous interlayer dielectric layer in some cases.
Meanwhile, a technique is known in which pores on the side wall surface of a groove formed by etching is sealed using a surfactant in a micelle state in wet cleaning after etching in a production method of semiconductor device using a porous low dielectric constant material (for example, see Japanese National-Phase Publication (JP-A) No. 2009-503879).
In addition, a technique is known in which the hydrophilicity and hydrophobicity of a low-k material is controlled by applying a polyvinyl alcohol-based amphiphilic polymer on the surface of the low-k material in a case in which the low-k material has a hydrophobic surface (for example, see International Publication No. WO 09/012184).
Moreover, a composition for semiconductor polishing containing a cationic polymer and a surfactant is known (for example, see Japanese Patent Application Laid-Open (JP-A) No. 2006-352042).